1. Field of the Invention
The present invention relates to a power-on reset circuit that outputs a reset signal when a supply voltage reaches a given voltage.
2. Description of the Related Art
A conventional power-on reset circuit is described. FIG. 4 is a diagram illustrating the conventional power-on reset circuit.
When a supply voltage VDD increases from 0 V, voltages of internal nodes N1 and N2 are also initially 0 V. When the supply voltage VDD becomes higher than a threshold voltage of an inverter 47, an output voltage VOUT becomes high, and the power-on reset circuit outputs a reset signal. Further, when the supply voltage VDD becomes higher than an absolute value of a threshold voltage of a PMOS transistor 41, the PMOS transistor 41 turns on, and the voltage of the internal node N1 becomes equal to the supply voltage VDD.
After that, when the supply voltage VDD further increases, the voltage of the internal node N1 also increases. However, the voltage of the internal node N1 is clamped to a total voltage (for example, 2Vtp) of absolute values of PMOS transistors 42 and 43. After that, when the supply voltage VDD becomes higher than a total voltage (for example, 3Vtp) of a threshold voltage (for example, Vtp) of a PMOS transistor 44 and the foregoing total voltage (for example, 2Vtp), the PMOS transistor 44 turns on, and the voltage of the internal node N2 becomes equal to the supply voltage VDD. The output voltage VOUT of the inverter 47 becomes low, and the power-on reset circuit stops outputting the reset signal.
After that, when the supply voltage VDD becomes low, and the supply voltage VDD becomes lower than a voltage resulting from subtracting an absolute value of a threshold voltage of a PMOS transistor 45 from the voltage of the internal node N2, the PMOS transistor 45 turns on. Then, the voltage of the internal node N2 becomes a voltage resulting from adding the absolute value of the threshold voltage of the PMOS transistor 45 to the supply voltage VDD. Hence, when the supply voltage VDD becomes 0 V, the voltage of the internal node N2 becomes equal to the absolute value of the threshold voltage of the PMOS transistor 45.
In this state, in the case where the supply voltage VDD becomes high again, when the supply voltage VDD becomes higher than a total voltage of the absolute values of the threshold voltages of the PMOS transistor 45 and the inverter 47, the power-on reset circuit outputs the reset signal (for example, refer to JP 11-068539 A).
However, in the related art, the power-on reset circuit continues to output the reset signal while the supply voltage VDD is lower than the total voltage of the absolute values of the threshold voltages of the PMOS transistors 42 and 44 after the power-on reset circuit outputs the reset signal. Hence, the power-on reset circuit cannot be applied to a semiconductor device that operates at supply voltage lower than the foregoing total voltage.